1. Field
This application relates to a buffer circuit and a control method thereof.
2. Description of Related Art
In general, output signal potential characteristic in a buffer circuit may greatly fluctuate due to fluctuations of a threshold value of MOS transistors caused by process fluctuation. Japanese Unexamined Patent Publication No. 9(1997)-93111 discloses a buffer circuit in which fluctuations of the output signal potential characteristic are suppressed.
The buffer circuit is provided with a first slew rate circuit and a second slew rate circuit. The first slew rate circuit has an input/output characteristic according to which, if an input potential of a signal input node is changed from a high level to a low level, a potential of a first output node rises rapidly from a low level, until the input signal potential becomes near ½ of a power supply potential, and a potential of the first output node rises slowly to a high level from a vicinity where the output signal potential at the output node dropped below ½ of the power supply potential. Further, the first slew rate circuit has an input/output characteristic according to which, if the input potential at a signal input node is changed from a low level to a high level, the potential at a first output node drops sharply from a high level to a low level.
The second slew rate circuit has an input/output characteristic according to which, if an input potential at a signal input node is changed from a high level to a low level, a potential at the second output node rises rapidly from a low level to a high level. Further, the second slew rate circuit has an input/output characteristic according to which, if an input potential at the signal input node is changed from a low level to a high level, a potential at the second output node drops rapidly from a high level until the input signal potential becomes near ½ of the power supply potential, and a potential at a second output node drops slowly approximately from where the output signal potential at the output node exceeds ½ of the power supply potential until it becomes a low level.
The above-described buffer circuit rapidly raises or drops the input waveforms of the output buffer circuit connected to the first and the second slew rate circuits up to ½ of the power supply voltage, depending on the input/output characteristic of the first and second slew rate circuits, after which, it slowly changes the input waveforms. In this buffer circuit, since the input waveforms of the output buffer circuit are rapidly raised or dropped up to ½ of the power supply voltage, and the output signal potential of the output buffer circuit exceeds an inversion region, it is possible to suppress the delay of the output signal potential with respect to the input potential.
An output buffer circuit 100 is known which is provided with a delay circuit 110 and an auxiliary driving circuit 120, as shown in FIG. 7, and in which a P-type channel transistor M71 and an N-type channel transistor M72 that constitute output switching elements are quickly changed from an OFF state to an ON state.
If an input signal inputted from an input terminal (IN) is changed from a high level to a low level in the above-described output buffer circuit 100, operation is carried out in the following manner. In this output buffer circuit 100, right after the input signal is changed from a high level to a low level, the gate voltage of the N-type channel transistor M74 is fixed to a low level voltage, so that the N-type channel transistor M74 enters an OFF state. At this time, the gate voltage of the P-type channel transistor M73 is fixed to a low level voltage, so that the P-type channel transistor M73 enters an ON state.
In addition, right after the input signal is changed from a high level to a low level, a delay circuit 110A inputs a low level delay signal obtained by delaying a high level input signal to a gate of the P-type channel transistor M75 in the auxiliary driving circuit 120. As a result, the gate voltage of the P-type channel transistor M75 is fixed to a low level voltage, so that the P-type channel transistor M75 enters an ON state. When the P-type channel transistor M73 and the P-type channel transistor M75 enter an ON state, respectively, a source current path L51 is formed as shown in the drawing. The source current path L51 extends from a power supply voltage Vdd to a gate of the N-type channel transistor M72 by passing through the P-type channel transistors M75 and M73.
Since the gate of the P-type channel transistor M76 is connected to a ground, the gate voltage of the transistor M76 is fixed to a low level voltage. As a result, the P-type channel transistor M76 is fixed to an ON state. When the P-type channel transistor M73 and the P-type channel transistor M76 enter an ON state, respectively, a source current path L52 is formed as shown in the drawing. The source current path L52 extends from the power supply voltage Vdd to a gate of the N-type channel transistor M72 by passing through the P-type channel transistors M76 and M73.
The forming of the source current path L52 in addition to the source current path L51 in the above-described output buffer circuit 100 helps increase the current driving capability of the source current path with respect to the N-type channel transistor M72. Consequently, the time required to approximate the gate voltage of the N-type channel transistor 72 to a threshold voltage is shortened. Thus, in the output buffer circuit 100, the time until the N-type channel transistor M72 is changed from an OFF state into an ON state, is shortened, with the threshold voltage set as a boundary.
On the other hand, in the above-described output buffer circuit 100, if the input signal is changed from a low level to a high level, a sink current path L62 is formed separately from a sink current path L61, by using the delay circuit 110B and the N-type channel transistor M80 of the auxiliary driving circuit 120. As a result, the current driving capability of the sink current path with respect to the P-type channel transistor M71 is increased. Consequently, the time required by the gate voltage of the P-type channel transistor M71 to approximate to a threshold voltage is shortened. Thus, similarly with the above-described N-type channel transistor M72, the time until the P-type channel transistor M71 is changed from an OFF state into an ON state is shortened. The symbols M78, M80 and M81 in the drawing show N-type channel transistors, respectively. Symbol 79 shows a P-type channel transistor.
However, in the above-described output buffer circuit 100, there may be cases that process fluctuation may cause fluctuations in the delay time of the respective delay circuits 110A and 110B and fluctuations in the threshold voltage of both transistors M75 and M80 of the auxiliary driving circuit 120.
In such a case, the fact that the timing at which the delay signals are outputted from the delay circuits 110 and 110B to respective gates of the transistors M75 and M80 differs, and the fact that the output timing of the respective delay signals differs may have an effect and may cause fluctuations in the time required to form the source current path L51 and the sink current path L62.
In the above-described output buffer circuit 100, when the time required to form the source current path L51 and the sink current path L62 fluctuates, it is believed that the time required by the gate voltage of transistors M71 and M72 to approximate to the threshold voltage fluctuates. Accordingly, in the above-described output buffer circuit 100, if the time required by the gate voltage of transistors M71 and M72 to approximate to the threshold voltage fluctuates, it is believed that the timing at which transistors M71 and M72 are changed from an OFF state to an ON state fluctuates, which may cause fluctuations in the slew rate.
When the slew rate fluctuates, it is believed that a response delay occurs in the output signal to be outputted from the output terminal (OUT) of the output buffer circuit 100, with respect to the input signal. Due to this, in the above-described output buffer circuit 100, the response delay in the output signal may have an effect, which may make the output characteristic become unstable.